Developments in semiconductor processing in recent years have steadily decreased the size of features or elements in semiconductor devices such as integrated circuits (ICs), thereby increasing the speed of the devices.
As the size of transistors is reduced, a limiting factor in the device speed is resistive-capacitive (RC) delay associated with electrically conducting/insulating interconnect structures. In particular, as IC technology continues to scale, the aspect ratio of metal lines increases and the intra-level line-to-line capacitance increasingly dominates over the inter-level capacitance.
One approach to reducing the RC delay involves depositing nitride around metal, local interconnect (LI) lines within a layer to reduce intra-level capacitance, while using another dielectric material, such as silicon dioxide (SiO2), to insulate the inter-level conducting layers. Subsequently, the inter-layer dielectric is patterned and etched to form vertical, borderless contacts or vias to the LI lines. By ‘borderless contact’ it is meant a metal, typically Tungsten (W), plug that makes contact with an underlying LI line without the use of a landing. That is, the borderless contact descends to an underlying structure that is no bigger in cross-section or diameter than the contact itself.
An example of a conventional interconnect structure formed on a substrate 100 using this approach is shown in FIGS. 1A and 1B. Referring to FIGS. 1A and 1B, a conventional method of forming a borderless contact begins with: (i) depositing a nitride 102 around local interconnect metal lines 104; (ii) covering the nitride with an inter-metal dielectric 106 (typically an oxide such as SiO2); and (iii) performing a contact etch to etch the inter-metal dielectric, followed by etching the nitride to expose the underlying LI line forming a contact opening 108.
The conventional approach or technology to forming borderless contact suffers from a number of difficulties or disadvantages. One disadvantage is that the contact etch itself is complex. Requiring an oxide etch selective to nitride to etch the inter-metal dielectric 106, followed by a nitride etch selective to oxide to expose the metal line 104. Etch chemistries and processes for etching oxide while stopping on nitride results in the formation of polymer deposits, which must be removed prior to the nitride etch. These deposits are removed either in-situ, that is in the same chamber or tool in which the contact etch is performed, or ex-situ in a separate chamber or tool. In-situ cleans are undesirable in that they impact chamber condition to the detriment of other processes performed in the chamber. Ex-situ cleans are also undesirable in that they require breaking vacuum and additional processing steps following the contact etch, slowing the fabrication of the devices or Fab throughput.
Another disadvantage of the conventional approach is that the high aspect ratio of openings in the nitride 102 between LI lines 104 results in problems with subsequent oxide 106 fill.
FIG. 1C is a diagram illustrating an electron microscope image of a sectional side view of a portion of a device formed on a substrate 110 showing a borderless contact 112 formed using a conventional method and extending through an inter-metal dielectric 114 to one of a number of LI lines 116. Referring to FIG. 1C it is seen that yet another disadvantage of the conventional approach is that nitride etch typically requires an overetch, which frequently results in the formation of a ‘tooth’ 118 on one or more sides of the LI lines 116, which may not fill during contact metal deposition, voids 120.
Accordingly, there is a need for a method or process of forming borderless contacts to underlying LI lines that eliminates the need for an in-situ clean during or following the contact etch. There is a further need for a process that substantially eliminates problems with oxide fill, and ‘tooth’ formation due to nitride overetch.
The present invention provides a solution to these and other problems, and offers further advantages over conventional processes.